Implementation of 16-Bit Vedic Multiplier Using Modified CSA

DOI

10.2991/978-94-6463-252-1_92How to use a DOI?

Keywords

Multiplier; Vedic Multiplier; Carry save adder; Modified carry save adder

Abstract

In this paper we have designed and implemented vedic multiplier using RCA, CSA and MCSA. The main component of DSP is the multiplier. The demand for high-speed multiplier circuitry is enormous. One of the most crucial factors in determining a multipliers effectiveness is speed, power and area. In order to accelerate multiplication using carry save adder, this paper aims based on the urdhva tiryagbhyam algorithm a Vedic multiplier is developed using CSA. One of the fast adder that can be utilised to lessen the total delay associated with addition is CSA. However, because of the dual RCA construction, carry save adder is not an area-efficient one. Using the carry save adder, RCA, half adders, full adder in Verilog HDL, a 16-bit Vedic multiplier is created using Modelsim to simulates and synthesised using Xilinx ISE 14.7. In this project implementation of Vedic Multiplier using carry save adder and comparing it with the Vedic multiplier using Ripple Carry Adder is performed. The synthesis result shows that CSA has 16% greater delay than Vedic multiplier using MCSA. CSA has 44% greater area than MCSA. MCSA has 15% reduced power than vedic multiplier using CSA.

Copyright

© 2023 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - B. Vanitha
AU  - S. Nagaraj
AU  - B. Sai Kumar
PY  - 2023
DA  - 2023/11/09
TI  - Implementation of 16-Bit Vedic Multiplier Using Modified CSA
BT  - Proceedings of the Second International Conference on Emerging Trends in Engineering (ICETE 2023)
PB  - Atlantis Press
SP  - 919
EP  - 927
SN  - 2352-5401
UR  - https://doi.org/10.2991/978-94-6463-252-1_92
DO  - 10.2991/978-94-6463-252-1_92
ID  - Vanitha2023
ER  -