Modeling and Simulation of Parasitic NPN ESD

DOI

10.2991/icimm-16.2016.75How to use a DOI?

Keywords

ESD; Parasitic NPN; SPICE; Macro Model; Snapback

Abstract

Electro-Static Discharge (ESD) is critical for the reliability of integrated circuits. Applying ESD model in circuit simulation could help to predict and avoid potential failure caused by ESD. This paper proposes a SPICE macro model for parasitic NPN ESD and related methods for extracting SPICE model parameters. The macro model utilizes the Taylor series to express collector current of NPN transistor under avalanche breakdown, and thus solves the problem of lack of convergence in prior models. The macro model's parameters are obtained by device measurement together with curve fitting. A device with parasitic NPN was fabricated in SMIC with 0.18um BCD process to verify the macro model. Chip tests indicate that the simulation results of the device's macro model exactly match with the real ESD characteristics of the device, which demonstrate the validity of the macro model for parasitic NPN ESD behavior in circuit simulations.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Haishi Wang
AU  - Feiyue Zhou
AU  - Hanfei Yang
AU  - Huaitian Liang
PY  - 2016/11
DA  - 2016/11
TI  - Modeling and Simulation of Parasitic NPN ESD
BT  - Proceedings of the 6th International Conference on Information Engineering for Mechanics and Materials
PB  - Atlantis Press
SP  - 413
EP  - 418
SN  - 2352-5401
UR  - https://doi.org/10.2991/icimm-16.2016.75
DO  - 10.2991/icimm-16.2016.75
ID  - Wang2016/11
ER  -