Simulation of 1.0 m CMOS Baseline Process at AEMD of Shanghai Jiao Tong University
Authors
Didi Ma, Xiaodong Wang, Yun Shen, Xiulan Cheng
Corresponding Author
Didi Ma
Available Online December 2015.
- DOI
- 10.2991/icmmcce-15.2015.497How to use a DOI?
- Keywords
- CMOS baseline process, semiconductor device, TCAD simulation, electrical test structure, six-inch baseline run.
- Abstract
A standard 1.0 m CMOS process are developed at AEMD (Center for Advanced Electronic Materials and Devices), which is a public platform about advanced micro-nano fabrication. The process supports 1.0 m twin well technology, with double poly-Si, double metal, and defines the standard process modules in the micro lab. Process and simulation data details are presented with the electrical test structure and device characterization for the first six-inch baseline run.
- Copyright
- © 2015, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Didi Ma AU - Xiaodong Wang AU - Yun Shen AU - Xiulan Cheng PY - 2015/12 DA - 2015/12 TI - Simulation of 1.0 m CMOS Baseline Process at AEMD of Shanghai Jiao Tong University BT - Proceedings of the 4th International Conference on Mechatronics, Materials, Chemistry and Computer Engineering 2015 PB - Atlantis Press SN - 2352-538X UR - https://doi.org/10.2991/icmmcce-15.2015.497 DO - 10.2991/icmmcce-15.2015.497 ID - Ma2015/12 ER -