Research on Traffic Monitoring Method of Elevated Road Based on DSP+FPGA
Rong-Bao Chen, Tian-Ze Fei, Ben-Xian Xiao, Peng Jiang, Dun-Hong Wang, Qian-Kun Zhang, Yu-Bing Pu, Ya-Feng Wu
Available Online December 2016.
- https://doi.org/10.2991/icwcsn-16.2017.36How to use a DOI?
- elevated road; DSP+FPGA architecture; background update; virtual coil; vehicle flow; limited height pole
- Along with the development of the urban rapid transit, the overhead traffic monitoring, and according to the traffic situation in a timely manner to make all kinds of control, management, and induced measures is one of the development trend of urban intelligent transportation. In this paper, the video image processing control platform to build is based on DSP + FPGA structure. DSP takes the core of video image processing tasks, FPGA as the data preprocessing unit, the completion of the interface logic, system interconnection and data channels. An elevated road traffic monitoring algorithm based on virtual detection coil is embedded in the management and control platform. First set up virtual coil in the video image as detection area and complete the image preprocessing. And then adopt the method of superposition averaging extract background. Using the adaptive background update background model, then adopt the background difference method to extract the foreground target; At the same time using a comprehensive color and texture shadow detection algorithm to eliminate the shadow, statistical vehicle flow; Through the traffic and extracting the average speed of adjustment on control platform limits the height of the mast, realizes the elevated road upward ramp traffic, restrictions, and shut down.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Rong-Bao Chen AU - Tian-Ze Fei AU - Ben-Xian Xiao AU - Peng Jiang AU - Dun-Hong Wang AU - Qian-Kun Zhang AU - Yu-Bing Pu AU - Ya-Feng Wu PY - 2016/12 DA - 2016/12 TI - Research on Traffic Monitoring Method of Elevated Road Based on DSP+FPGA PB - Atlantis Press SP - 164 EP - 169 SN - 2352-538X UR - https://doi.org/10.2991/icwcsn-16.2017.36 DO - https://doi.org/10.2991/icwcsn-16.2017.36 ID - Chen2016/12 ER -