A New BIST Scheme with Encoding Logic to Achieve Complete Fault Coverage

DOI

10.2991/iea-15.2015.11How to use a DOI?

Keywords

Built-in Self Test(BIST); test application time; fault coverage

Abstract

Built-in Self Test(BIST)has been proved as one of the effective design for testability techniques, where on-chip test architectures are designed to test the digital circuits themselves. To reduce test application time and improve fault coverage, A deterministic Built-in Self Test(BIST) technique that can get complete fault coverage without using any storage device is proposed in this paper. The test architecture contains a novel on chip encoding logic that generates all required test vectors in real time. Experimental results show that the proposed technique requires much less test application time to achieve complete fault coverage for all testable stuck-at faults with reasonable hardware cost.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Zhang Ling
AU  - Mei Junjin
AU  - Wang Guan-zhong
AU  - Li Tonghan
PY  - 2015/09
DA  - 2015/09
TI  - A New BIST Scheme with Encoding Logic to Achieve Complete Fault Coverage
BT  - Proceedings of the AASRI International Conference on Industrial Electronics and Applications (2015)
PB  - Atlantis Press
SP  - 40
EP  - 43
SN  - 2352-5401
UR  - https://doi.org/10.2991/iea-15.2015.11
DO  - 10.2991/iea-15.2015.11
ID  - Ling2015/09
ER  -