A Hybrid Low-Cost PLL Test Scheme based on BIST Methodology
Authors
Zhikuang Cai, Shixuan Que, Tingting Liu, Haobo Xu
Corresponding Author
Zhikuang Cai
Available Online April 2015.
- DOI
- 10.2991/isrme-15.2015.75How to use a DOI?
- Keywords
- PLL; BIST; jitter; fault model; production test; parametric test
- Abstract
In this paper, a hybrid built-in self-test (BIST) scheme is firstly proposed for phase-locked loop (PLL) production test and performance characterization. The scheme combines the structure test and function test in production test operation. The former is to detect hard faults and the latter is used to improve the soft fault coverage. Jitter measurement is selected as a typical parameter test in performance characterization mode, which includes vernier delay line (VDL) to measure timing jitter and undersampling technology to measure cycle-cycle jitter. The goal of the scheme is to enable complete production quality test and exact performance characterization.
- Copyright
- © 2015, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Zhikuang Cai AU - Shixuan Que AU - Tingting Liu AU - Haobo Xu PY - 2015/04 DA - 2015/04 TI - A Hybrid Low-Cost PLL Test Scheme based on BIST Methodology BT - Proceedings of the 2015 International Conference on Intelligent Systems Research and Mechatronics Engineering PB - Atlantis Press SP - 354 EP - 357 SN - 1951-6851 UR - https://doi.org/10.2991/isrme-15.2015.75 DO - 10.2991/isrme-15.2015.75 ID - Cai2015/04 ER -