An Experiment Design for Measuring Response Time of FPGA Logic Cell

DOI

10.2991/jimec-18.2018.27How to use a DOI?

Keywords

FPGA, Response time, Measurement

Abstract

Response time of digital device affects signal competitions and hazards seriously, and these competitions and hazards often cause instability and error of instruments, so response time of FPGA logic cell is a very important parameter of the chip, especially in high speed FPGA signal processing system. Because response time of most logic devices is very short, its measurement is always difficult. In this paper, an ingenious method of measuring response time of FPGA logic cell is put forward. A measurement experiment is designed, and its measuring principle is analyzed. The experiment testified the correctness of the method of response time measuring.

Copyright

© 2019, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Zhou Huanyin
AU  - Xu Mei
AU  - Hu Jiewei
AU  - Xie Yanhui
AU  - Lv Ziyong
AU  - He Gaokui
PY  - 2018/12
DA  - 2018/12
TI  - An Experiment Design for Measuring Response Time of FPGA Logic Cell
BT  - Proceedings of the 2018 3rd Joint International Information Technology，Mechanical and Electronic Engineering Conference (JIMEC 2018)
PB  - Atlantis Press
SP  - 129
EP  - 132
SN  - 2589-4943
UR  - https://doi.org/10.2991/jimec-18.2018.27
DO  - 10.2991/jimec-18.2018.27
ID  - Huanyin2018/12
ER  -