An Ultra Low-power Low-Voltage Programmable Frequency Divider for PLL Frequency Synthesizer

DOI

10.2991/jimec-18.2018.41How to use a DOI?

Keywords

Frequency divider; Low-power; Low-voltage; Phase switching; 0.13um COMS

Abstract

In this paper, an ultra low-voltage frequency divider for PLL (Phase Locked Loop) was designed using 0.13um CMOS process with 0.6V power supply. The frequency divider employs divide by 15/16 dual modulus prescaler based on phase switching, two programmable counters and the control module for prescaler. The operation frequency of this divider is from 0.8GHz to 2.2GHz. The power dissipation of the programmable frequency divider is only equal to 603uW. Additionally, a PMOS VCO oscillator from 1.51~1.70GHz was designed to cooperate with the programmable frequency divider which consumes 660uW from 0.6V supply voltage.

Copyright

© 2019, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Chenggang Yan
AU  - Jianhui Wu
AU  - Chen Hu
PY  - 2018/12
DA  - 2018/12
TI  - An Ultra Low-power Low-Voltage Programmable Frequency Divider for PLL Frequency Synthesizer
BT  - Proceedings of the 2018 3rd Joint International Information Technology，Mechanical and Electronic Engineering Conference (JIMEC 2018)
PB  - Atlantis Press
SP  - 191
EP  - 194
SN  - 2589-4943
UR  - https://doi.org/10.2991/jimec-18.2018.41
DO  - 10.2991/jimec-18.2018.41
ID  - Yan2018/12
ER  -