FPGA Implementation of JPEG-LS Remote Sensing Image Coding Algorithm

DOI

10.2991/macmc-17.2018.10How to use a DOI?

Keywords

FPGA; JPEG-LS; VHDL; Integrated Rate

Abstract

In this paper, through the research of JPEG-LS encoding algorithm, the algorithm is implemented with FPGA chip XC4VSX55-12ff1148, which is implemented on the ise14.7 development platform of Xilinx company. The algorithm adopts modular design idea,from the image data collection and storage, variable update, Golomb encoding, regular mode encoding, run length mode encoding, encoding output and storage to achieve modular, each module is described in VHDL language. Finally, the coding rate, synthesis rate and chip utilization of single image coding are obtained.

Copyright

© 2018, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Hairong Wang
PY  - 2018/01
DA  - 2018/01
TI  - FPGA Implementation of JPEG-LS Remote Sensing Image Coding Algorithm
BT  - Proceedings of the 2017 4th International Conference on Machinery, Materials and Computer (MACMC 2017)
PB  - Atlantis Press
SP  - 39
EP  - 44
SN  - 2352-5401
UR  - https://doi.org/10.2991/macmc-17.2018.10
DO  - 10.2991/macmc-17.2018.10
ID  - Wang2018/01
ER  -