Efficient Implementation of Precise Exception for Processor Based on Pre-detection
- 10.2991/meic-15.2015.95How to use a DOI?
- exception flag; pre-detection; dedicated module; NOP instruction; processor
Embedded systems have higher requirements on real-time performance of processor, and exception, which can interrupt normal execution of program, will decrease the processor performance. For improving the processor exception handling efficiency, a precise exception handling method for embedded pipeline processor is proposed in this paper. When the precise exception occurs in any pipeline stage, the precise exception flag is set valid immediately and advanced to the next pipeline stage. Based on pre-detection on that exception flag, a single-cycle NOP instruction is provided for the processor by a dedicated hardware module. That separates the processor from spending large number of clock cycles requesting main instruction memory for instructions which will be flushed in the process of exception handling. This method has been implemented in a SPARC V8 processor which has successfully taped out. Test results of chip show that the precise exception detection and response efficiency is increased by 35.47% without increasing the processor critical path. The proposed method can be used to improve response efficiency of the precise exception at low hardware overheads.
- © 2015, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Qingyu Chen AU - Erjuan Zhu AU - Longsheng Wu PY - 2015/04 DA - 2015/04 TI - Efficient Implementation of Precise Exception for Processor Based on Pre-detection BT - Proceedings of the 2015 International Conference on Mechatronics, Electronic, Industrial and Control Engineering PB - Atlantis Press SP - 410 EP - 413 SN - 2352-5401 UR - https://doi.org/10.2991/meic-15.2015.95 DO - 10.2991/meic-15.2015.95 ID - Chen2015/04 ER -