A high speed Montgomery processor of 256-bit on FPGA
- Xiaonan Zhang, Xiuze Dong
- Corresponding Author
- Xiaonan Zhang
Available Online November 2016.
- https://doi.org/10.2991/aest-16.2016.41How to use a DOI?
- ECC; Montgomery modular multiplication algorithm; multi-step operation.
- To improve the speed of modular multiplication operation on ECC processor over GF (p), the paper presented a novel hardware implementation of Montgomery algorithm. Based on analyzing basic Montgomery modular multiplication algorithm, this work applied multi-step operation to Montgomery algorithm, which can accelerate speed by reducing the number of clocks. Simulation with Modelsim indicates that a completion of modular multiplication requires only 16 clock circles. Finally, the design of hardware architectures was evaluated on Altera Stratix III families. By following the new design concept, the multiplier structure can reach to a higher performance. Compared with other modular multiplier, the computation time of improved modular multiplier is lesser, decreasing 42% and reaching to 0.2 µs. It is estimated that the computation of a 256-bit scalar point multiplication over GF(p) would take about 0.76 ms.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Xiaonan Zhang AU - Xiuze Dong PY - 2016/11 DA - 2016/11 TI - A high speed Montgomery processor of 256-bit on FPGA BT - 2016 International Conference on Advanced Electronic Science and Technology (AEST 2016) PB - Atlantis Press SN - 1951-6851 UR - https://doi.org/10.2991/aest-16.2016.41 DO - https://doi.org/10.2991/aest-16.2016.41 ID - Zhang2016/11 ER -