A Double Node Upset Tolerant Memory Cell
Xin Liu, Guang Mao, Le Zhong, Lei Xie, Renhua Yang, Gang Dai
Available Online September 2016.
- https://doi.org/10.2991/amitp-16.2016.40How to use a DOI?
- Double node upset, single node upset, dual interlock cell, memory cell.
- As we enter the deep submicron era, the steadily shrinking feature sizes make charge sharing much easier among physically adjacent nodes in integrated circuits, which ultimately results in DNU (Double Nodes Upset). In this paper, we propose a 16-transistor memory cell. Hspice simulation shows this cell maintains its original logic status under SNU (Single Node Upset) and DNU, while DICE (Dual Interlock CEll) and Quatro-10T cell may fail. Besides, the 16T cell reduces the circuit area by 33.33%, compared to the other two DNU tolerant cells, Delta DICE and DONUT.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Xin Liu AU - Guang Mao AU - Le Zhong AU - Lei Xie AU - Renhua Yang AU - Gang Dai PY - 2016/09 DA - 2016/09 TI - A Double Node Upset Tolerant Memory Cell PB - Atlantis Press SP - 203 EP - 207 SN - 2352-538X UR - https://doi.org/10.2991/amitp-16.2016.40 DO - https://doi.org/10.2991/amitp-16.2016.40 ID - Liu2016/09 ER -