NAND Flash Bad Block Management Research Based On FPGA
Guohui Wu, Yongjie Hu, Jian Wu
Available Online May 2015.
- 10.2991/asei-15.2015.33How to use a DOI?
- NAND Flash, bad block management, mapping table
For the requirement of the stability in large-capacity data storage, this paper proposes a management method of bad block based on setting up block address mapping table in the interior of FPGA. While operating the NAND Flash , we can take advantage of the mapping tables to shield inherent bad blocks and new produced blocks .The research proved that the method can avoid the operation of bad blocks efficiently and improve the reliability of data shortage greatly.
- © 2015, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Guohui Wu AU - Yongjie Hu AU - Jian Wu PY - 2015/05 DA - 2015/05 TI - NAND Flash Bad Block Management Research Based On FPGA BT - Proceedings of the 2015 International conference on Applied Science and Engineering Innovation PB - Atlantis Press SP - 149 EP - 152 SN - 2352-5401 UR - https://doi.org/10.2991/asei-15.2015.33 DO - 10.2991/asei-15.2015.33 ID - Wu2015/05 ER -