A Method for Automatically Implementing FPGA-basedPipelined Microprocessors

DOI

10.2991/cnct-16.2017.65How to use a DOI?

Keywords

Pipeline, Automatic,Stall, Bypass, Multi-cycle

Abstract

This paper presents a method of automatically generating the Verilog implementation of pipelined micro-processors. Based on the RTL descriptions of instructions, all types of hazards in pipelining are addressed optimally, especially in avoiding redundancy, reducing resource utilization and improving instruction throughput. Moreover, out-of-order execution mechanism is adopted in order to support multi-cycle instructions more efficiently. Besides, all the multiplexers and logics of control signals are analyzed and produced all by the method. The synthesized implementations of both pipelined controllers and datapaths are generated automatically, based on non-fixed architectures. A case study based on MIPS architecture not only explains the framework from input to simulation, but also illustrates the method gains almost equal performance with manual work.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Yu-xiang ZENG
AU  - Han WAN
AU  - Bo JIANG
AU  - Xiao-peng GAO
PY  - 2016/12
DA  - 2016/12
TI  - A Method for Automatically Implementing FPGA-basedPipelined Microprocessors
BT  - Proceedings of the International Conference on Computer Networks and Communication Technology (CNCT 2016)
PB  - Atlantis Press
SP  - 467
EP  - 474
SN  - 2352-538X
UR  - https://doi.org/10.2991/cnct-16.2017.65
DO  - 10.2991/cnct-16.2017.65
ID  - ZENG2016/12
ER  -