An improved low power Viterbi decoder in System-on-Chips

DOI

10.2991/eeeis-16.2017.39How to use a DOI?

Keywords

Viterbi decoder; add-compare-select(ACS); trace-back; low power.

Abstract

The (2,1,7) convolutional codes have become the standard encoding method of satellite communication system. Based on an optimized structure, a low power (2,1,7) Viterbi decoder with trace-back length of 32 is presented in this paper. New structure of add-compare-select(ACS) unit is exploited to reduce power consumption. Instead of using register-exchange(RE) and register banks, trace-back that consumes less power and the power-saving RAM are used. Our proposed Viterbi decoder consumes about 28.8k gates using Global Foundry 65 nm technology. The power consumption of our design is about 8.8mw at 250MHz.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Download article (PDF)

TY  - CONF
AU  - Rong Gao
AU  - Li-Xing Tang
AU  - Shan Cao
PY  - 2016/12
DA  - 2016/12
TI  - An improved low power Viterbi decoder in System-on-Chips
BT  - Proceedings of the 2nd Annual International Conference on Electronics, Electrical Engineering and Information Science (EEEIS 2016)
PB  - Atlantis Press
SP  - 299
EP  - 306
SN  - 2352-5401
UR  - https://doi.org/10.2991/eeeis-16.2017.39
DO  - 10.2991/eeeis-16.2017.39
ID  - Gao2016/12
ER  -