A Cache Utility Monitor for Multi-core Processor

DOI

10.2991/icwcsn-16.2017.113How to use a DOI?

Keywords

Multicore; Shared cache; Cache partitioning.

Abstract

In recent years, high performance computing systems have obtained more processing cores and shared a last level cache (LLC). Now, the problem to the existing cache partitioning techniques is that they give each core the number of cache ways according to their need, these schemes have the potential to realize significant performance increases, yet for most part they do not consider LLC energy saving. In this paper, we design and realize a multi-processing processor monitor. Through a utility monitor we calculate the number of hits and misses when allocate different cache ways to each application. In other words, we use utility monitors to track the access by each core to characterize each thread's use of the cache. Dynamically give each core the number of ways based on the performance to achieve its highest utilization. On gem5, we run Parsec benchmarks as our multi-threaded application. We output the numbers of misses for all possible number of ways, and find the number of associativity to achieve its highest utilization. By analysing experimental results, cache miss rate decreases with the increasing of the cache capacity.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Juan Fang
AU  - Yan-Jin Cheng
AU  - Min Cai
AU  - Ze-Qing Chang
PY  - 2016/12
DA  - 2016/12
TI  - A Cache Utility Monitor for Multi-core Processor
BT  - Proceedings of the 3rd International Conference on Wireless Communication and Sensor Networks (WCSN 2016)
PB  - Atlantis Press
SP  - 561
EP  - 565
SN  - 2352-538X
UR  - https://doi.org/10.2991/icwcsn-16.2017.113
DO  - 10.2991/icwcsn-16.2017.113
ID  - Fang2016/12
ER  -