Optimization of SRAM in 28nm HPM Technology

DOI

10.2991/jiaet-18.2018.51How to use a DOI?

Keywords

LPSR SRAM; Redundancy logic; Power on/off states

Abstract

This paper presents an optimized SRAM that is repairable and consumes less power dissipation. To increase the percent of good SRAMs per wafer, redundancy logic and e-fuse box are added to SRAM, thereby building SR SRAM. In order to reduce power dissipation, power on/off states and isolation logic are introduced to SR SRAM, consequently constructing LPSR SRAM. Also the testing methodology of the SoC which has been successfully implemented Chartered 28nm HPM process is discussed. The testing results indicate that 25% of power saving is obtained to the LPSR SRAM64K×32 and the percent of the good LPSR SRAM64K×32s per wafer is increased by 20%.

Copyright

© 2018, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Qingjun Zhou
AU  - Jing Xing
AU  - Yamei Zhang
PY  - 2018/03
DA  - 2018/03
TI  - Optimization of SRAM in 28nm HPM Technology
BT  - Proceedings of the 2018 Joint International Advanced Engineering and Technology Research Conference (JIAET 2018)
PB  - Atlantis Press
SP  - 290
EP  - 295
SN  - 2352-5401
UR  - https://doi.org/10.2991/jiaet-18.2018.51
DO  - 10.2991/jiaet-18.2018.51
ID  - Zhou2018/03
ER  -