Design of high-accuracy decimal frequency divider with Verilog-HDL

DOI

10.2991/ipemec-15.2015.16How to use a DOI?

Keywords

Decimal frequency divider; Verilog-HDL; DDS

Abstract

This paper presents a more complex algorithm with Verilog-HDL, which based on the dual-modulus preseted decimal frequency divider. This algorithm can not only increase the accuracy of decimal frequency divider. , but also can be used to divide a clock. Simulations are conducted to analyze the characteristics of the decimal frequency divider and DDS divider. The results shows that the divider can satisfy the requirements of design.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Shaowei Ma
AU  - Baolu Guan
AU  - Ligang Hou
PY  - 2015/05
DA  - 2015/05
TI  - Design of high-accuracy decimal frequency divider with Verilog-HDL
BT  - Proceedings of the 2015 International Power, Electronics and Materials Engineering Conference
PB  - Atlantis Press
SP  - 80
EP  - 85
SN  - 2352-5401
UR  - https://doi.org/10.2991/ipemec-15.2015.16
DO  - 10.2991/ipemec-15.2015.16
ID  - Ma2015/05
ER  -