Proceedings of the 2015 International Power, Electronics and Materials Engineering Conference

Design of high-accuracy decimal frequency divider with Verilog-HDL

Authors
Shaowei Ma, Baolu Guan, Ligang Hou
Corresponding Author
Shaowei Ma
Available Online May 2015.
DOI
https://doi.org/10.2991/ipemec-15.2015.16How to use a DOI?
Keywords
Decimal frequency divider; Verilog-HDL; DDS
Abstract
This paper presents a more complex algorithm with Verilog-HDL, which based on the dual-modulus preseted decimal frequency divider. This algorithm can not only increase the accuracy of decimal frequency divider. , but also can be used to divide a clock. Simulations are conducted to analyze the characteristics of the decimal frequency divider and DDS divider. The results shows that the divider can satisfy the requirements of design.
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Proceedings
2015 International Power, Electronics and Materials Engineering Conference
Part of series
Advances in Engineering Research
Publication Date
May 2015
ISBN
978-94-62520-73-8
ISSN
2352-5401
DOI
https://doi.org/10.2991/ipemec-15.2015.16How to use a DOI?
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Shaowei Ma
AU  - Baolu Guan
AU  - Ligang Hou
PY  - 2015/05
DA  - 2015/05
TI  - Design of high-accuracy decimal frequency divider with Verilog-HDL
BT  - 2015 International Power, Electronics and Materials Engineering Conference
PB  - Atlantis Press
SN  - 2352-5401
UR  - https://doi.org/10.2991/ipemec-15.2015.16
DO  - https://doi.org/10.2991/ipemec-15.2015.16
ID  - Ma2015/05
ER  -