A parallel HEVC encoder scheme based on Multi-core platform

DOI

10.2991/nceece-15.2016.74How to use a DOI?

Keywords

HEVC; multi-core platform; parallel processing; frame-level; CTB-level

Abstract

In this paper, we propose a parallel HEVC encoder scheme based on multi-core platform, which provides maximized parallel scalability by exploiting two-level parallelism, namely, the frame level parallelism and the CTB level parallelism. Inspired by the intra-CTB row level parallelism of WPP in HEVC, we investigate the inter-frame CTB prediction dependency to its reference CTBs, and find the inter-CTB correlation. Using this inter-correlation, we divide a frame into CTB units and create CTB-row level coding threads when their corresponding reference CTBs are available. Each thread is bonded to a processing core, therefore, both intra- and inter-CTB rows can be encoded in parallel. Moreover, we introduce a priority scheduling mechanism to control the coding threads. Experiments on Tilera-Gx36 multi-core platform show that, compared with serial execution, the proposed method achieves 3.6 and 4.3 times speedup for 1080P and 720P video sequences, respectively.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Hu Jun
PY  - 2015/12
DA  - 2015/12
TI  - A parallel HEVC encoder scheme based on Multi-core platform
BT  - Proceedings of the 2015 4th National Conference on Electrical, Electronics and Computer Engineering
PB  - Atlantis Press
SP  - 375
EP  - 381
SN  - 2352-5401
UR  - https://doi.org/10.2991/nceece-15.2016.74
DO  - 10.2991/nceece-15.2016.74
ID  - Jun2015/12
ER  -