A 6GHz Input Bandwidth Track-and-Hold circuit in HBT Technology
Authors
Yujun Yang, Yao Li, Yu Zhou, Jun’an Zhang, Jun Liu, Jing Li, Dongbing Fu, Guangbing Chen
Corresponding Author
Yujun Yang
Available Online December 2015.
- DOI
- 10.2991/nceece-15.2016.234How to use a DOI?
- Keywords
- analog integrated circuits; analog to digital converter; heterojunction bipolar transistor; spurious-noise-free dynamic range; track and hold amplifier.
- Abstract
This paper presents the design of a 6GHz track-and hold circuit with input bandwidth. The track-and hold circuit adopts the design simulation of HBT process, able to work at a sampling frequency of 2 GHz, the highest sampling frequency can reach about 2 GHz. The SFDR of the track-and hold circuit can reach 64dB (simulation work at 2 GHz),The track-and hold circuit provides more than 66 dB hold –mode SFDR3 for 0 to 2GHz 1Vpp input signals at 2GHz. Early product parameters of the track-and hold circuit (working in 2 GHz sampling frequency) are as follows: the SFDR parameter can be achieved 64 dB.
- Copyright
- © 2016, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Yujun Yang AU - Yao Li AU - Yu Zhou AU - Jun’an Zhang AU - Jun Liu AU - Jing Li AU - Dongbing Fu AU - Guangbing Chen PY - 2015/12 DA - 2015/12 TI - A 6GHz Input Bandwidth Track-and-Hold circuit in HBT Technology BT - Proceedings of the 2015 4th National Conference on Electrical, Electronics and Computer Engineering PB - Atlantis Press SP - 1327 EP - 1332 SN - 2352-5401 UR - https://doi.org/10.2991/nceece-15.2016.234 DO - 10.2991/nceece-15.2016.234 ID - Yang2015/12 ER -